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Apr 01, 2023

Subject Code & Title : EEEE3098 VLSI Laboratory Simulation & Layout Software
This Laboratory forms part of the assessment for the Integrated Circuits and Systems module
EEEE3098. It must be written as a formal report and submitted via Moodle no later than This report is 30% of the overall marks for this module with the usual penalties for late submission.
EEEE3098 VLSI Laboratory – Simulation & Layout Software Assignment – UK.

Introduction :
Very Large Scale Integration design today is carried out totally by use of a computer. The Computer Aided Design (CAD) route for full custom VLSI design is typically as follows:

1.Schematic : System drawn using schematic symbols such as NAND gates, flip-flops etc.

2.High Level Simulation: System simulated either at the gate or behavioural level

3.Cell Design : Individual cells are designed and simulated at the transistor level using SPICE or a similar circuit level simulator. This is called the Pre-layout simulation

4.Cell Layout : CAD layout used to layout individual transistors in each cell”Polygon pusher”

5.Design Rule Check :The various features drawn are checked for minimum size and separation (DRC)

6.Net list Extract : Capacitance, resistance and the netlist is now extracted automatically from the layout

7.Electrical Rule Check : The circuit is now checked for electrical violations (ERC), ie outputs short circuit

8.Simulation : The circuit is now re-simulated with SPICE, with the parasitics calculated in (6) above included. This is called the Post layout simulation.

9.System Layout : Complete chip is laid out and if necessary steps 5, 6, 7 and are repeated at the system level.

10.Verification : The layout is converted either to a transistor or a gate description. This is then compared with the original schematic description in (1) above.

11.Mask Generation : The layout, usually described in a text form, is then converted into a photo mask. One of the standard text layout forms is CIF (Caltech Intermediate Format)

Computers today can handle designs with many thousands of transistors. The package being used in this exercise is freeware software.

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