A special communication network protocol uses the sequence 01111110 to represents the beginning of a message (digital message consists of sequence of 0s and 1s). This flag must be unique, as a consequence, the most five 1s in sequence may appear anywhere else in the message. Since this is not realistic for normal message content, a trick called zero-insertion is used. The normal message, which can contain strings of 1s longer than 5, enters into the zero-insertion converter. When a fifth 1 in sequence appears on the input sequence, the converter will insert a 0 in the stream in the output. For example

The input sequence is:

01111100111111100001011110101

The zero-insertion converter will generate the sequence:

0111110001111101100001011110101

Part I  Understand the Function

In this part of the procedure, you will need to use an example to understand the function of the zero-insertion converter.

1. Identify the input and output of the zero-insertion converter

2. Walk through bit by bit (consider each bit takes one clock cycle) the function of the converter using the example 01111100111111100001011110101 as input sequence.

3. Draw a flowchart of the zero-insertion converter, include this flowchart in your final project report

4. Use the example you walked through in step 2 to test your flowchart and make any necessary revision/correction.

5. You should at this point notice that a sub-circuit for this converter must be designed to inform the circuit that supplies the converter the input to stall and not apply a new input for one clock cycle. This means that other than the output message sequence, you will need another sequence as the output to feedback to the circuit that supplies the converter the input to know when to stall. (You may assume that the circuit that supplies the converter the input sequence is already designed and does stall correctly according to the indication provided by the converter to do so.)

Part II  Translate the function into State Machine Description

6. Find the state diagram for the converter based on the flowchart, and identified input and outputs. You must include this state diagram in your final project report.

7. Use the example sequence from Part I to verify the correctness of your state diagram and make any revision/correction as necessary. Include you steps on how you verify your state diagram, any corrections your made, and your final version of the state diagram

8. Find the state table for the converter circuit. Verify the correctness of it.

9. Made a state assignment.

10. Complete the sequential circuit design process to come up with the circuit implementation.

Part III  Find an Implementation of the circuit

11. With all the information you identified in Part II, you are now ready to implement the design in Verilog.

12. Write a Verilog module called csc340teamproject to implement your circuit design.

13. Write a test bench for the Verilog module csc340teamproject and make sure to include test cases that will thoroughly test your implementation.

14. Simulate the circuit using ISim and analyze the resulting waveform.

15. Take full screenshots of all Verilog source codes and the resulting simulation waveform to be included in the lab report.

Note: At least 3 different input sequences (with stalls) to test your design. Demonstrate from all the sequences test results show that your design functions correctly. One of the test sequences must include a sequence of 11 co